1. Field of the Invention
The present invention relates to a semiconductor device having a Schottky source/drain transistor.
2. Description of the Related Art
A Schottky source/drain transistor technology of producing a transistor's source/drain portion formed of a metal material instead of an impurity diffusion layer is proposed. By using this structure, a parasitic resistance in source and drain regions can be reduced, and a shallow junction (Schottky junction) can be formed.
In addition, because impurities are not used for a source/drain, there is no need for carrying out a high temperature annealing process for activation, and a manufacturing process can be significantly simplified.
Furthermore, a Schottky barrier exists at a source portion, an OFF current is restricted, and a short channel effect can be restricted (the transistor can be minimized).
On the other hand, a problem to be solved with this transistor is to reduce a Schottky contact resistance. One solution to this problem includes a work function control technology for a source/drain material. For example, there is proposed a method of using a metal or silicide (such as ErSi2) with a small work function is used for an nMOS source/drain and using a metal or silicide (such as PtSi) with a large work function for a pMOS source/drain.
By using this technology, a Schottky barrier height at nMOSFET can be set to about 0.28 eV, and a Schottky barrier height at pMOSFET can be set to about 0.22 eV. Therefore, it is possible to form a metal silicide source/drain with a certain low Schottky contact resistance in both of nMOSFET and PMOSFET. However, these values are not insufficient in order to obtain a sufficient high current, and further Schottky barrier reduction is required. Unfortunately, only with a work function control of a metal, it has been difficult to further reduce a Schottky barrier because the barrier is affected by a Fermi level pinning effect.
There is proposed a metal source/drain transistor technology of forming a thin insulation film on a Schottky junction interface in order to reduce the Schottky barrier while avoiding influence caused by the Fermi level pinning effect (Daniel Connelly et al., Silicon Nano-technology, P. 122), (2003).
When a thin insulation film (for example, SiN film of 1 nm or less) is formed on the interface of the Schottky junction which is sandwiched between a Si-channel and a metal source/drain, a low Schottky barrier can be realized while restraining the Fermi level pinning effect. However, a conventional silicide process cannot be used to form this transistor. Therefore, it has been impossible to easily form a small transistor having a gate length of a nano-level. Dimensions of a transistor reported by Connelly are very large (about 20 μm in gate length), and a semiconductor substrate is used as a gate. Thus, a gate electrode edge and a source/drain have not been self-aligned.